Field
This disclosure relates generally to electrical circuits, and more specifically, to a voltage regulator with load current prediction and method therefor.
Related Art
In integrated circuits, a pin-less voltage regulator is a class of voltage regulators that does not require an off-chip capacitor for complying with load transient response and stability specifications. The use of pin-less regulators in integrated circuit (IC) products provides advantages such as cost reduction, reduced number of pins on the IC, and reduced dependency from external devices and board parasitics.
FIG. 1 illustrates, in schematic diagram form, a pin-less voltage regulator 10 in accordance with the prior art. FIG. 1 shows an example implementation of a switched biasing control circuit 12 connected to N-channel transistor 14. N-channel transistor 14 has an intrinsic gate-source capacitance represented by capacitor 16 in FIG. 1. Capacitor 16 also represents all other capacitances connected to the gate of N-channel transistor 14. Biasing control circuit 12 is composed of two comparators 18 and 20 in a window comparison configuration. Comparator 18 receives a reference voltage labeled VREF_LO and controls the gate of P-channel transistor 22 in response to a comparison of VREF_LO with a feedback voltage generated from an output voltage VOUT. Comparator 20 receives a reference voltage labeled VREF_HI and provides a bias voltage to control the gate of N-channel transistor 28 in response to a comparison of VREF_HI with the feedback voltage generated from output voltage VOUT. N-channel transistor 14 drives a variable load that can be modelled by a resistance 30 and a capacitance 32. Biasing control circuit 12 controls the conductivity of N-channel transistor 14 in response to a changing load sensed via the feedback of VOUT. The reference voltages are used to set the voltage of VOUT. Reference voltage VREF_LO is lower than reference voltage VREF_HI. When output voltage VOUT is above the VREF_HI value, N-channel transistor 28 is on and current source 26 starts discharging the capacitance 16. When output voltage VOUT is below reference voltage VREF_LO value, P-channel transistor 22 is on and current source 24 charges capacitance 16.
It is desirable that voltage regulator 10 provides a stable power supply voltage within a certain margin. Generally, the output voltage variation, specified to accommodate process variations and input voltage/load transient variations, is a percentage of nominal supply voltage. As the semiconductor technology progresses to smaller technology process nodes (mainly from 55 nm and smaller), the nominal supply voltage is reduced. For example, at a 90 nm (nanometer) technology node, the power supply voltage may be 1.25 volts and at the 28 nm technology node the power supply voltage may be 0.9 volts. As a consequence, the voltage variation (in absolute value, not in percentage) was also reduced at the newer technology nodes, reducing the margin for regulator accuracy and voltage variation due to load steps. In addition, the low power techniques (power gating, clock gating, back biasing technique) greatly increase the load transient current steps. Using these low power techniques, the load transient current steps may reach up to 1000×.
If implemented in the newer technologies, voltage regulator 10 may not be able to detect and react to the faster load current steps. Also, for a fixed gate voltage if the source voltage VDD decreases, the current flowing through N-channel transistor 14 will increase to minimize source voltage drop. However, it takes time for the VOUT feedback voltage to be reacted to by biasing control 12, thus allowing a significant output voltage drop before bias circuit 12 can react to the load change.